1. Field of the Invention
The invention relates in general to a method for fabricating a thin film transistor (TFT), and more particularly to a method for fabricating a low temperature polysilicon (LTPS) thin film transistor.
2. Description of the Related Art
Recently, because of rapid development in technology, display panels have been generally applied in the portable appliances such as laptops, personal digital assistants (PDAs), and cellular phones. The display panel includes an amorphous silicon (a-Si) thin film transistor (TFT) display panel and a low temperature polysilicon (LTPS) TFT display panel. The LTPS TFT display panel is superior to the amorphous silicon TFT display panel due to the amorphous silicon layer of the LTPS TFT display panel is transformed into a polysilicon layer by laser annealing so that the TFT electron mobility can be improved efficiently. Therefore, the characteristic of higher electron mobility enables the LTPS to integrate driving circuit and integrated circuit (IC) in the TFT display panel and facilitates the flexibility of design in the display panel and the circuits without additional external circuit. As a result, the LTPS TFT display panel is going to be a star in the future.
FIGS. 1A to 1I are cross-section views showing a conventional process for fabricating a low temperature polysilicon thin-film transistor. First, referring to FIG. 1A, a glass substrate 11 is provided and then a silicon dioxide (SiO2) layer 12 is formed over the glass substrate 11. An amorphous silicon layer 13 is formed over the SiO2 layer 12 subsequently. Besides, the thickness of the amorphous silicon layer 13 is preferably about 500 angstrom (Å).
The laser-annealing step is used to transform the amorphous silicon layer 13 into a polysilicon layer 14, which is shown as FIG. 1B. The next step is to remove portions of the polysilicon layer 14 to form at least one polysilicon island 14a on the SiO2 layer 12 as shown in FIG. 1C.
Next, both ends of the polysilicon island 14a are doped to respectively form a heavily doped n type (n+) ohmic contact layer 15 and a residual polysilicon layer 14b. Each of the n+ ohmic contact layers 15 is closely connected to the lateral residual polysilicon island 14b at both ends as shown in FIG. 1D. A first insulating layer 16 is then formed over the SiO2 layer 12 to cover the n+ ohmic contact layers 15 as well as the residual polysilicon island 14b. 
Both ends of the residual polysilicon island 14b are doped where to respectively form a lightly doped n type (n−) ohmic contact layer 17. Meanwhile, a polysilicon channel area 14c is also formed; thus, each of the n− ohmic contact layers 17 is in the position between the polysilicon channel area 14c and the n+ ohmic contact layer 15 as shown in FIG. 1E. Agate 18, which is disposed at a location opposite to the polysilicon channel area 14c, is then formed on the first insulating layer 16. Each of the n− ohmic contact layers 17 also functions as a lightly doped drain (LDD) herein.
Next, a second insulating layer 19 is formed on the first insulating layer 16 to cover the gate 18 as shown in FIG. 1F. There are a first contact hole 20a and a second contact hole 20b penetrating through the second insulating layer 19 as well as the first insulating layer 16, respectively. Besides, the first contact hole 20a and the second contact hole 20b are selectively located near the lateral ends of the gate 18 so that portions of the n+ ohmic contact layers 17 are exposed.
FIG. 1G illustrates the next step that a source 21a and a drain 21b are respectively formed within the first contact hole 20a and the second contact hole 20b and cover portions of the second insulating layer 19 near both ends of the gate 18. The source 21a and the drain 21b are electricity connected to the n+ ohmic contact layers 17 via the first contact hole 20a as well as the second contact hole 20b, respectively.
Referring to FIG. 1H, a passivation layer 22 is formed over the second insulating layer 19 to cover the source 21a and the drain 21b. In addition, there is a third contact hole 23 penetrating through the passivation layer 22 so that a portion of the source 21a is explored. An indium tin oxide (ITO) electrode 24 is then formed within the third contact hole 23 and on a portion of the passivation 22; therefore, the source 21a electrically connects to the ITO electron 24 via the third contact hole 23. The cross-section view of the finished LTPS-TFT 10 is shown in FIG. 1I.
FIG. 1J illustrates the condition when the amorphous layer 13 is partially melted by laser annealing into a solid amorphous silicon layer 13a and a liquid amorphous silicon layer 13b. Typically, the phenomenon of heterogeneous nucleation occurs at the solid a-Si layer 13a/liquid a-Si layer 13b interface. Therefore, a number of polysilicon seeds 14d are formed and irregularly distributed on the rough surface of the solid amorphous silicon layer 13a. The irregularly distributed polysilicon seeds 14d consequently serve as nucleation sites during the crystallization process The amorphous silicon layer 13b crystallizes heterogeneously, which results in forming of substantially distinct polysilicon grain sizes due to the irregularly distributed nucleation sites. As a result, the electron mobility of TFT can not be improved effectively.
FIG. 1K illustrates the condition when the amorphous layer 13 is completely melted into a liquid amorphous layer 13c. From the perspective of thermodynamic, free energy of the solid amorphous layer 13 is smaller than that of liquid amorphous layer 13c. The liquid amorphous layer 13c is therefore in a so-called super-cooling condition. Thus, homogeneous nucleation occurs within the liquid amorphous silicon layer 13c. The polysilicon seeds 14e with almost identical grains size are formed gradually with even distribution. The amorphous silicon 13c is then homogeneously crystallized as the polysilicon layer. Even though the uniformality of the grain size is greatly improved, the grain size is generally small, which does not benefit the electron mobility of TFT.
In the light of practical experiences, the best solution for overcoming the problems mentioned above is to identify a super lateral growth (SLG), which is the best depth of liquid amorphous silicon layer. Referring back to FIG. 1J, when the depth of liquid amorphous silicon layer 13b is equal to the super lateral growth. The distances between polysilicon seeds 14d would be adequate to form large grains. Besides, the polysilicon seeds 14d can also be evenly distributed at the solid a-Si layer/liquid a-Si layer interface during the step of laser annealing; however, it is very difficult to achieve the goal. Hence, it is desirable to develop a technique to convert the amorphous silicon layer into the polysilicon layer over which large grains are distributed uniformly.